Semiconductor integrated circuit chips are constructed as dice on wafers. A typical wafer material is crystalline silicon. Wafers are cut from single crystal silicon ingots grown from polysilicon by means of, for example, Czochralski method (CZ) crystal growth. CZ wafers are preferred for VLSI applications as they can withstand high thermal stresses and are able to offer an internal gettering mechanism that can remove unwanted impurities from device structures on a wafer surface. This also gives the wafer a uniform internal structure based on silicon's diamond cubic lattice structure. Although the diamond cubic lattice provides strength and rigidity to the wafer, defects in the crystal lattice, for example, slip dislocations, can adversely affect fabricated circuit electrical properties leading to a reduction in the number of good dice per wafer. A schematic representation of the diamond cubic lattice structure of silicon is depicted in FIG. 1A.
The atoms in a crystal lattice structure of a silicon wafer align with each other to form planes traversing the wafer in multiple directions. Three principal planes, and their respective orientations, (100), (110), and (111), are shown in FIGS. 1B-1D. Equivalent planes are designated by braces, for example, {111}, {110}, and {100}, represent equivalents to the (111), (110), and (100) principal planes, respectively. In many applications, orienting the crystal to an s equivalent plane will achieve the same result as aligning it to its principal plane. Many structural properties of silicon depend on its planar orientation. Plane (111) has the highest number of atoms per unit of surface area and is said to be packed very tightly. This high atomic density results in a greater number of available charge carriers, which allows for faster current propagation. Concurrently, the more tightly a crystal plane is packed, the higher the probability that slip dislocations and other defects will occur. These defects can cause parasitic currents as well as charge leaks that can lead to poor performance and device failure.
To help identify crystalline planes, wafers are typically fabricated with a notch or flat relative to a selected crystalline plane. Throughout the integrated circuit (IC) manufacturing industry, automated wafer handling equipment utilize these notches or flats, fabricated in the wafers, to align the wafer, allowing devices on a wafer to be aligned with a specific crystal plane. A development in the art has been the shift to formation of semiconductor devices on a silicon wafer wherein the devices are aligned so that source-drain current in those devices travel along a {110} plane, usually the (110) plane. As indicated above, a {110} plane has a more closely packed atomic structure than a {100} plane, which coincides with a higher charge mobility in devices aligned such that current flows along the (110) plane, as compared to devices aligned such that current flows along the (100) plane. A result of this characteristic of silicon crystals is faster data throughput where device current is aligned along the (110) plane. Several U.S. patents teach the alignment of devices to a (110) plane, for example, U.S. Pat. No. 5,729,045, to Buynosik, entitled “Field Effect Transistor With Higher Mobility,” discloses a method of increasing the performance of an FET by aligning channel current with the (110) crystal plane of a (100) wafer. However, the Buynosik device is inappropriate for contemporary high-density device fabrication since any defects present in the crystal lattice can have severe deleterious effects on an electronic device. Buynosik teaches neither how to eliminate or deal with the lattice defects.
In fact, an ongoing trend in microelectronics devices is a reduction in device size. Concurrently, with the scaling down of IC devices, device current paths are smaller and device currents are decreased. One result is that crystal defects and unintentional currents are proportionally larger as IC devices become smaller.
One approach to reducing the problems associated with the defects discussed above is to improve the quality of the wafer itself. One method of improving the wafer is through an epitaxial deposition wherein a thin layer of single crystal silicon material is deposited on the surface of a silicon crystal substrate. These wafers are commonly known as epi wafers. Experimentation has shown that these types of wafers have higher yields than standard wafers.
In FIG. 2, a silicon wafer 201 is shown with a single MOSFET device including a source 205, a drain 207, and a gate 209, wherein a source-drain current channel is aligned to a primary flat 203. The primary flat is typically aligned with the (110) plane and the arrow (vector) indicates a [110] direction, which is normal to the (110) plane. Most commercially available epitaxial wafers are manufactured with the primary flat aligned with the (110) plane. Traditionally, fabrication equipment aligns a wafer using a primary flat (or notch) as a reference. With a primary flat aligned with a (110) plane, devices constructed from these epitaxial wafers have current channels that are aligned along the (110) plane. With larger scale devices, this has not been a problem since any defects formed had little influence on device performance and could be ignored. However, with design rules ever decreasing, any defects present in the crystal lattice can start to have severe deleterious effects on an electronic device.